The above-referenced co-pending U.S. patent application Ser. No. 382,388, describes a semiconductor processing technique for manufacturing an edge-connectable integrated circuit structure, in which a substantially planar semiconductor substrate that contains a densely compacted arrangement of semiconductor devices, such as a photodiode array, is interconnected with side edge portions of a plurality or stack of extremely thin semiconductor wafers in which signal processing electronics for the arrangement are formed. For this purpose, the rear surface of the substrate is provided with an array of conductive bumps associated with the physical disposition of the photodiodes, which bumps are to be conductively joined with corresponding metallic bumps along side edge portions of the stack of thin wafers that contain the signal processing electronics.
The inability to use conventional photolithographic processing to form the interconnect bumps along side edges of the wafer is successfully remedied in accordance with the invention detailed in the '388 application by forming trenches in the semiconductor wafer material that intersect doped semiconductor regions of the wafer's signal processing circuitry. The required metallic bumps to be mated with those of the photodiode array are then electroplated on the exposed side edge surfaces of the doped semiconductor regions in the trench portions of the wafer. After this electroplating process, the wafer is backlapped, for example by mechanical grinding and/or chemical etch, until the material removal plane intersects the trench and thereby severs the `thinned` wafer into separate dice, each of which has a row of side edge-connection bumps for connection with corresponding bumps of the substrate. The severed dice may then be robotically seized, transported into adjacent alignment with and then conductively joined to the bumps of the substrate, with each signal processing die being oriented orthogonally to the planar surface of the substrate such that its side edge bumps are connected to the bumps of the photodiode-containing substrate.
Advantageously, the side edge processing technique described in the '388 application makes it possible to house all of the signal processing electronics for an individual row of photodiodes of a focal plane array in a single, relatively thin wafer having a thickness on the order of only one to two mils, so that the individual light responsive elements of the focal plane array can be of reduced size, thereby providing a considerably enhanced resolution optical signal processor. For example, for a 128.times.128 photodiode array, a two mil thickness of an individual die results in an array resolution of less than two mils per pixel, which is an order of magnitude smaller of that of a conventional printed circuit board approach.
Now although the trench sidewall electroplating mechanism described in the '388 application facilitates forming edge connections on a very thin wafer, which is desirable from a packaging standpoint, the wafer itself is fragile and subject to breaking when handled or processed by conventional methods. In particular, as described in the above-referenced '091 application, when a very thin processed wafer has been separated into individual dice, and its underlying handle layer is then removed, leaving only the thin wafer and an adjoining (oxide) layer, handling of the resulting structure (which may have a diameter up to five inches) is very difficult and may damage the individual devices.